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AMD Mobile Serial VID Dual-Phase
Fixed-Frequency Controller
Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse that is associated with this acknowledge bit. The
device that acknowledges has to pull down the SVD
line during the acknowledge clock pulse so the SVD
line is stable LOW during the HIGH period of the
acknowledge-related clock pulse. Setup and hold times
must be taken into account. See Figure 11. Figure 12
shows the SVI bus data transfer summary.
Command Byte
A complete command consists of a START condition
(S) followed by the MAX17009’s slave address and a
data phase, followed by a STOP condition (P).
DATA OUTPUT
SMPS Applications Information
Duty-Cycle Limits
Minimum Input Voltage
The minimum input operating voltage (dropout voltage)
is restricted by stability requirements, not the minimum
off-time (t OFF(MIN) ). The MAX17009 does not include
slope compensation, so the controller becomes unsta-
ble with duty cycles greater than 50% per phase:
V IN(MIN) ≥ 2 x V OUT(MAX)
However, the controller can briefly operate with duty
cycles over 50% during heavy load transients.
BY MASTER
D7
D6
D0
NOT ACKNOWLEDGE
DATA OUTPUT
BY MAX17009
ACKNOWLEDGE
SVC FROM
MASTER
1
2
8
9
S
CLK1
CLK2
CLK8
CLK9
START
CONDITION
ACKNOWLEDGE
CLOCK PULSE
Figure 11. SVI Bus Acknowledge
S
T
A
R
T
S
T
O
P
S
SLAVE ADDRESS
A
C
K
SET DAC AND PSI_L
A
C
K
P
Figure 12. SVI Bus Data Transfer Summary
40
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